The present invention relates generally to methods and systems for decoding signals encoded with a multi-state encoding architecture in a high-speed communication system and, more particularly, the invention relates to a method and a system for decoding the trellis code specified in the IEEE 802.3ab standard for Gigabit Ethernet (1000BASE-T) with a minimum of computational complexity and propagation delays in the logic circuits.
In recent years, local area network (LAN) applications have become more and more prevalent as a means for providing local interconnect between personal computer systems, work stations and servers. Because of the breadth of its installed base, the 10BASE-T implementation of Ethernet remains the most pervasive if not the dominant, network technology for LANs. However, as the need to exchange information becomes more and more imperative, and as the scope and size of the information being exchanged increases, higher and higher speeds (greater bandwidth) are required from network interconnect technologies. Among the highspeed LAN technologies currently available, fast Ethernet, commonly termed 100BASE-T, has emerged as the clear technological choice. Fast Ethernet technology provides a smooth, non-disruptive evolution from the 10 megabit per second (Mbps) performance of 10BASE-T applications to the 100 Mbps performance of 100BASE-T. The growing use of 100BASE-T interconnections between servers and desktops is creating a definite need for an even higher speed network technology at the backbone and server level.
One of the more suitable solutions to this need has been proposed in the IEEE 802.3ab standard for gigabit ethernet, also termed 1000BASE-T. Gigabit ethernet is defined as able to provide 1 gigabit per second (Gbps) bandwidth in combination with the simplicity of an ethernet architecture, at a lower cost than other technologies of comparable speed. Moreover, gigabit ethernet offers a smooth, seamless upgrade path for present 10BASE-T or 100BASE-T ethernet installations.
In order to obtain the requisite gigabit performance levels, gigabit ethernet transceivers are interconnected with a multi-pair transmission channel architecture. In particular, transceivers are interconnected using four separate pairs of twisted Category-5 copper wires. Gigabit communication, in practice, involves the simultaneous, parallel transmission of information signals, with each signal conveying information at a rate of 250 megabits per second (Mb/s). Simultaneous, parallel transmission of four information signals over four twisted wire pairs poses substantial challenges to bidirectional communication transceivers, even though the data rate on any one wire pair is xe2x80x9conlyxe2x80x9d 250 Mbps.
In particular, the gigabit ethernet standard requires that digital information being processed for transmission be symbolically represented in accordance with a five-level pulse amplitude modulation scheme (PAM-5) and encoded in accordance with an 8-state Trellis coding methodology. Coded information is then communicated over a multi-dimensional parallel transmission channel to a designated receiver, where the original information must be extracted (demodulated) from a multi-level signal. In gigabit Ethernet, it is important to note that it is the concatenation of signal samples received simultaneously on all four twisted pair lines of the channel that defines a symbol. Thus, demodulator/decoder architectures must be implemented with a degree of computational complexity that allows them to accommodate not only the xe2x80x9cstate widthxe2x80x9d of Trellis coded signals, but also the xe2x80x9cdimensional depthxe2x80x9d represented by the transmission channel.
Computational complexity is not the only challenge presented to modern gigabit capable communication devices. A perhaps greater challenge is that the complex computations required to process xe2x80x9cdeepxe2x80x9d and xe2x80x9cwidexe2x80x9d signal representations must be performed in an almost vanishingly small period of time. For example, in gigabit applications, each of the four-dimensional signal samples, formed by the four signals received simultaneously over the four twisted wire pairs, must be efficiently decoded within a particular allocated symbol time window of about 8 nanoseconds.
Successfully accomplishing the multitude of sequential processing operations required to decode gigabit signal samples within an 8 nanosecond window requires that the switching capabilities of the integrated circuit technology from which the transceiver is constructed be pushed to almost its fundamental limits. If performed in conventional fashion, sequential signal processing operations necessary for signal decoding and demodulation would result in a propagation delay through the logic circuits that would exceed the clock period, rendering the transceiver circuit non-functional. Fundamentally, then, the challenge imposed by timing constraints must be addressed if gigabit Ethernet is to retain its viability and achieve the same reputation for accurate and robust operation enjoyed by its 10BASE-T and 100BASE-T siblings.
In addition to the challenges imposed by decoding and demodulating multilevel signal samples, transceiver systems must also be able to deal with intersymbol interference (ISI) introduced by transmission channel artifacts as well as by modulation and pulse shaping components in the transmission path of a remote transceiver system. During the demodulation and decoding process of Trellis coded information, ISI components are introduced by either means must also be considered and compensated, further expanding the computational complexity and thus, system latency of the transceiver system. Without a transceiver system capable of efficient, high-speed signal decoding as well as simultaneous ISI compensation, gigabit ethernet would likely not remain a viable concept.
The present invention is directed to a system and method for decoding information coded in accordance with a multi-level encoding scheme by computing a distance between a received word from a codeword. Codewords are formed from a concatenation of symbols from a multi-level symbol alphabet, with the symbols selected from two disjoint one-dimensional symbol subsets X and Y. A received word is represented by L inputs, with L representing the number of dimensions of a multi-dimensional communication channel. Each of the L inputs uniquely corresponds to one of the L dimensions.
A set of 1-dimensional (1D) errors is produced from the L inputs, with each of the 1-dimensional errors representing a distance metric between a respective one of the L inputs and a symbol in one of the two disjoint one-dimensional symbol subsets. 1-dimensional errors are combined in order to produce a set of L-dimensional errors such that each of the L-dimensional errors represents a distance between the received word and a nearest codeword among an ordered plurality of codewords.
In one aspect of the invention, each of the L inputs is sliced with respect to each of the two disjoint symbol subsets X and Y in order to produce a set of X-based errors, a set of Y-based errors and corresponding sets of X-based and Y-based decisions. The sets of X-based and Y-based errors form the set of 1-dimensional errors, while the sets of X-based and Y-based decisions forming a set of 1-dimensional decisions. Each of the X-based and Y-based decisions corresponds to a symbol, in a corresponding symbol subset, closest in distance (value) to one of the L inputs. Each of the 1-dimensional errors represents a distance metric between a corresponding 1-dimensional decision and the respective one of the L inputs.
In an additional aspect of the invention, each of the L inputs is sliced with respect to each of the two disjoint symbol subsets X and Y in order to produce a set of 1-dimensional decisions. Each of the L inputs is further sliced with respect to a symbol-set including all of the symbols of the two disjoint symbol subsets in order to produce a set of hard decisions. The X-based and Y-based 1-dimensional decisions are combined with a set of hard decisions in order to produce a set of 1-dimensional errors, with each of the 1-dimensional errors representing a distance metric between a corresponding 1-dimensional decision and a respective one of the L inputs. The slicers and the combination circuitry which produces the 1-dimensional error terms are implemented as an integrated circuit look-up table. Combination operations and error term definition are performed by consulting an appropriate entry in a table of entries. Error terms so developed are expressed in digital representation having one bit.
In another aspect of the present invention, 1-dimensional errors are combined in a first set of adders in order to produce a set of 2-dimensional errors. A second set of adders combines the 2-dimensional errors in order to produce intermediate L-dimensional errors, with the intermediate L-dimensional errors being arranged into pairs of errors such that the pairs of errors correspond one-to-one to the contents of an ordered plurality of codewords. A minimum-select module determines a minimum for each of the pairs of errors. Once determined, the minima are defined as the L-dimensional errors.
In a particular aspect of the invention, the decoding system and method is implemented in a bidirectional communication system in which transceivers are coupled together over a four twisted wire pair transmission channel. Each of the wire pairs corresponds to an input such that L equals four. Signals transmitted and received over the four twisted wire pair transmission channel are encoded in accordance with a multi-state trellis encoding architecture.